1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems including an accelerator capable of accelerated execution of some subgraphs within a program.
2. Description of the Prior Art
It is known to provide data processing systems with accelerator hardware operating to accelerate execution of some program subgraphs within a program. As an example, it may be that a program has a particular need to perform a complex operation a large number of times during its normal operation, such as decrypt a large quantity of data from a stream of data using a decryption technique which repeatedly executes the same piece of program code. It is possible that this program code may be written as a sequence of individual program instructions that are sequentially separately executed by a general purpose execution unit. However, it is known to provide special purpose accelerator hardware in such circumstances that can operate to provide hardware support for accelerated execution of such specific processing requirements.
One approach is to add such special purpose accelerated hardware and then add specific instructions to the instruction set of the apparatus to represent the complex operation which is to be performed by the accelerator hardware. As an example, a general purpose instruction set could be augmented by the addition of specific decryption instructions which when encountered would be executed by the decryption acceleration hardware. This approach suffers from a number of disadvantages.
A program written to include the new decryption program instructions in place of the previous sequence of standard program instructions is no longer capable of being executed on a system which does not include the accelerator hardware. Thus, several versions of a computer program may need to be written, tested and maintained, each targeted at different hardware platforms which may or may not contain the hardware accelerator. Furthermore, different versions of a hardware accelerator may be present in different implementations with varying capabilities requiring different programs to be written to reflect those differing capabilities. The special purpose accelerator added to implement the new special purpose instructions also represents a significant design investment and requires the testing and validation for each variant that was produced.
It is also known to provide data processing systems with the capability to examine the stream of program instructions that are being executed to determine if they can be modified/re-ordered or otherwise changed to run in a more efficient fashion. An example is a system which can combine two individual program instructions to form a single fused instruction that results in the same overall processing operation but is able to execute more rapidly. Whilst such systems are effective, the hardware and complexity overhead associated with seeking to identify program instructions that can be safely fused in this way is considerable and a disadvantage.